AMD explains how CPUs will implement 3D Vertical Cache

Posted on Friday, Jun 11 2021 @ 16:16 CEST by Thomas De Maesschalck
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Earlier this month, AMD teased an upcoming Ryzen 5000 series processor with 3D Vertical Cache technology. This is a new technique that promises to deliver up to 15 percent higher performance for some use cases, like video games. In a new YouTube video, AMD provides some details on how 3D Vertical Cache is implemented in the processor design.

If you don't like listening to a long video, TechPowerUp has a summary over here. Apparently, AMD made quite a number of changes to the CPU design. The new chips promise lower power consumption, lower temperatures, and lower latency:
The added information explains that there is no usage of microbumps - instead, there is a perfect alignment between the bottom layer (with the CCX) and the top layer (the L3 cache) which enables the bonding process to occur naturally via the TSVs (Through Silicon Vias) already present in the silicon, in a zero-gap manner, between both halves of the CPU-cache sandwich. To enable this, AMD flipped the CCX upside down (the core complex now faces the bottom of the chip, instead of the top), shaved 95% of the silicon on top of the upside-down core complexes, and then attaches the 3D V-Cache chips on top of this formation. This also has the added bonus of decreasing the distance between the L3 cache and the CCX (the distance between both in the Z axis is around 1,000 times smaller than if the L3 cache was deployed in the classical X axis), which decreases power consumption, temperatures, and latency, allowing for further increases to system performance.

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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