TSMC made its announcement at an industry event on Thursday in the U.S., its first in-person tech symposium in two years. The Taiwanese chip titan said its 2nm tech will be based on "nanosheet transistor architecture" to deliver significant improvements in performance and power efficiency. Nanosheet architecture is a completely different infrastructure from the Finfet infrastructure used for 5nm chips, currently the most advanced on the market. Such new tech requires massive investments to make available.Production of 3nm chips is expected to start in the second half of this year. The company's N3 roadmap will include five nodes over the course of three years. All 3nm processes from TSMC will use FinFlex, a new technique that promises higher performance, energy efficiency, density, and design flexibility.
Compared with N3E, TSMC's N2 node promises a 25-30 percent reduction in power use or 10-15 percent higher performance. However, the improvement in chip density is not that great. TSMC mentions a gain of "higher than 10 percent", which is pretty low versus previous generations.