The provision of a half-node step allows designers to improve performance and reduce the size of their designs by up to 19 percent. This can result in more die per wafer and more than 20 percent reduction in cost-per-die for certain designs, TSMC said.More details at EE Times.
The 80-nm process is a lithographic shrink of TSMC’s 90-nm process technology. As a consequence, this node supports most of the 90-nm libraries and intellectual property from TSMC and third-parties, requiring only simple re-characterization using 80-nm transistor models. Design rules are also a linear shrink from 90-nm.
ATI and NVIDIA to use 80nm process
Posted on Thursday, Jan 19 2006 @ 01:30 CET by Thomas De Maesschalck