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AMD Zen core architecture promises higher single-threaded performance

Posted on Tuesday, April 28 2015 @ 14:18:59 CEST by


Please ignore the information below as AMD has announced that these leaked slides are fabricated.

"These slides contain fabricated content and were not generated by or on behalf of AMD" - AMD spokesperson


A slide revealing details about AMD's Zen core has been leaked at the forum of German tech site Planet3DNow! The slide is supposedly part of a presentation that will be revealed at AMD's Financial Analyst Day and is under embargo until May 6, 2015.

The diagram reveals the major architectural changes between Excavator and Zen. Zen breaks away from the Bulldozer architecture family by returning to a more Phenom-like design with a monolithic decode unit and equally large, single integer and floating point units. This should result in better single-threaded performance, an area in which the Bulldozer design severely lacks.

The first processors based on Zen are expected in 2016.
To begin with, Zen features monolithic fetch and decode units. On Bulldozer, two cores inside a module featured dedicated decode and integer units with shared floating-point units. On Zen, there's a monolithic decode unit, and single integer and floating points. The integer unit has 6 pipelines, compared to 4 per core on Bulldozer. The floating point unit has two large 256-bit FMAC (fused-multiply accumulate) units, compared to two 128-bit ones on Bulldozer. The core has a dedicated 512 KB L2 cache. This may be much smaller than the 2 MB per module on Bulldozer, but also indicate that the core is able to push through things fast enough to not need cushioning by a cache (much like Intel's Haswell architecture featuring just 256 KB per core). In a typical multi-core Zen chip, the cores will converge at a large last-level cache, which routes data between them to the processor's uncore, which will feature a DDR4 IMC and a PCI-Express 3.0 root complex.
AMD Zen Core

Via: TPU



 



 

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