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Latest news on DV Hardware - Older stories
Intel video cards to use Xe branding December 12, 2018 - 18:49
NVIDIA GeForce 417.35 WHQL driver fixes some bugs December 12, 2018 - 16:58
Intel teases Sunny Cove, Willow Cove and Golden Cove architectures December 12, 2018 - 16:19
Intel provides update about Optane roadmap December 12, 2018 - 15:54
Intel Gen11 iGPU promises to be almost as fast as AMD Vega 8 December 12, 2018 - 15:52
Intel teases 10nm Sunny Cove CPU architecture December 12, 2018 - 15:46
Intel Foveros enables logic-on-logic 3D stacking December 12, 2018 - 15:39
SpaceX delay demonstration of Crewed Dragon test flight to January 17 December 12, 2018 - 12:34
Intel teases high-performance Sunnycove core December 12, 2018 - 12:25
Intel using MRAM in commercial products December 12, 2018 - 12:20
Inno3D shows two-faced iChill X3 Jekyll for NVIDIA GeForce RTX line December 12, 2018 - 12:14
10 companies buy 35 percent of server processors December 12, 2018 - 10:51
512GB SSD to cost the same as 1TB HDD by late 2019? December 12, 2018 - 10:35
Apple macOS 10.14 Mojave cripples NVIDIA GPU support December 12, 2018 - 10:29
Supermicro: Study finds no evidence of Chinese espionage December 11, 2018 - 16:54
AMD Radeon Software Adrenalin 2019 feature set leaks December 11, 2018 - 16:45
Qualcomm axes its ARM server chip division December 11, 2018 - 14:15
Google ditching Google+ earlier than expected after new data leak December 11, 2018 - 13:59
Microsoft IntelliMouse gets new in-house sensor and RGB LED December 11, 2018 - 13:45
First photo appears of GeForce RTX 2060 from Gigabyte December 11, 2018 - 11:22

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Intel Architecture Day – Foveros, Sunny Cove and Gen11 Graphics Coming Soon December 12, 2018 - 16:11
Intel Unveils 10nm Sunny Cove CPU Architecture With Gen11 Graphics, Major Perfor December 12, 2018 - 15:55
Intel Foveros To Usher In Industry First 3D Stacked System On A Chip Designs December 12, 2018 - 15:55
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Posted on Wednesday, December 12 2018 @ 18:49:32 CET by Thomas De Maesschalck
INTC logo
One more thing from the Intel Architecture Day. The company provided a glimpse at its future discrete video card plans and announced it will use Xe branding (which is of course very easy to type!). This brandname will replace the "Gen12" name that was previously used.

The first Xe products are expected in 2020 and this will include everything from integrated solutions to datacenter products. There will be two different architectures; one optimized for client applications and one optimized for the datacenter market.

Intel GPU roadmap
(comments?)

Posted on Wednesday, December 12 2018 @ 16:58:20 CET by Thomas De Maesschalck
NVDA logo
NVIDIA published its GeForce 417.35 WHQL driver, you can grab it over here. This version adds support for DLSS in FFXV, has some new or updated 3D Vision profiles and fixes some bugs.
Provides the optimal gaming experience for the release of Deep Learning Super Sampling (DLSS) beta in Final Fantasy XV: Windows Edition

Bug fixes:
  • [SLI][TITAN Xp]: SLI is disabled by default after installing the driver. [200471881]
  • [TITAN V][NVIDIA Control Panel]: The Workstation->Manage GPU Utilization page appears when it shouldn’t. [200470813]
  • [Rocket League]: The game launches to a white screen with audio in the background and then crashes. [2451530]
  • [Battlefield V: Day0 97][Ansel]: After being moved all the way to the left, the Ansel field-of view (FoV) slider stops following the click-and-drag mouse movement. [2438857]
  • [Hitman 2 Silent assassin]: There is flickering texture corruption in the game. [200472315]
  • [Notebook][3D games]: Frame rate of 3D games may drop to under 30 fps on notebooks. [2456653]

  • (comments?)

    Posted on Wednesday, December 12 2018 @ 16:19:37 CET by Thomas De Maesschalck
    INTC logo
    At the Architecture Day, Intel presented an updated roadmap for the Core and Atom product lines. Quite a lot of changes here, the 10nm Cannonlake has effectively been dumped, instead we'll see a new chip based on the Sunny Cove design in 2019.

    Keep in mind that the codenames below are the microarchitecture names, the actual chips these cores will be used in will likely still have Lake names. For example, Intel said at the event that Ice Lake will use Sunny Cove cores.

    Sunny Cove is a 10nm product and it will be the biggest change to the Core lineup since the launch of Skylake. You can expect higher single-threaded performance, new instructions, and improved scalability.

    In 2020 we can expect Willow Cove, this architecture delivers a redesigned cache new transistor optimizations and new security features. Golden Cove will follow in 2021, that architecture will feature single-threaded performance optimization, better AI performance, a networking/5G performance uplift, and more security features.

    AnandTech has a nice write-up with a ton of details over here.

    INTC architecture roadmap
    (comments?)

    Posted on Wednesday, December 12 2018 @ 15:54:20 CET by Thomas De Maesschalck
    INTC logo
    Next, there's an update about the Optane roadmap. Here's a summary of what Intel had to say at its Architecture Day:
    Memory and Storage: Intel discussed updates on Intel® Optane™ technology and the products based upon that technology. Intel® Optane™ DC persistent memory is a new product that converges memory-like performance with the data persistence and large capacity of storage. The revolutionary technology brings more data closer to the CPU for faster processing of bigger data sets like those used in AI and large databases. Its large capacity and data persistence reduces the need to make time-consuming trips to storage, which can improve workload performance. Intel Optane DC persistent memory delivers cache line (64B) reads to the CPU. On average, the average idle read latency with Optane persistent memory is expected to be about 350 nanoseconds when applications direct the read operation to Optane persistent memory, or when the requested data is not cached in DRAM. For scale, an Optane DC SSD has an average idle read latency of about 10,000 nanoseconds (10 microseconds), a remarkable improvement.2 In cases where requested data is in DRAM, either cached by the CPU's memory controller or directed by the application, memory sub-system responsiveness is expected to be identical to DRAM (<100 nanoseconds).

    The company also showed how SSDs based on Intel's 1 Terabit QLC NAND die move more bulk data from HDDs to SSDs, allowing faster access to that data.

    The combination of Intel Optane SSDs with QLC NAND SSDs will enable lower latency access to data used most frequently. Taken together, these platform and memory advances complete the memory and storage hierarchy providing the right set of choices for systems and applications.

    (comments?)

    Posted on Wednesday, December 12 2018 @ 15:52:37 CET by Thomas De Maesschalck
    INTC logo
    Intel also talked about its graphics plans at its Architecture Day. One of the key elements here is that the chip giant's Gen10 graphics will not be adopted, instead the firm is jumping straight to Gen11. This new generation features 64 improved execution units (EUs), which is significantly more than the 24 offered by Gen9 graphics. Intel claims Gen11 will be able to break the 1 teraflops barrier. At least on paper, this makes it a rival to AMD's Vega 8 integrated graphics (AMD Ryzen 3 2200G).

    The first 10nm processors with Gen11 integrated graphcis are expected in 2019, with the introduction of Sunny Cove. Besides a lot more EUs and architectural improvements, Gen11 will feature tile-based rendering, Coarse Pixel Shading (similar to NVIDIA's Variable Pixel Shading), a new HEVC encoder design, and Adaptive Sync support.
    Next-Generation Graphics: Intel unveiled new Gen11 integrated graphics with 64 enhanced execution units, more than double previous Intel Gen9 graphics (24 EUs), designed to break the 1 TFLOPS barrier. The new integrated graphics will be delivered in 10nm-based processors beginning in 2019.

    The new integrated graphics architecture is expected to double the computing performance-per-clock compared to Intel Gen9 graphics. With >1 TFLOPS performance capability, this architecture is designed to increase game playability. At the event, Intel showed Gen11 graphics nearly doubling the performance of a popular photo recognition application when compared to Intel's Gen9 graphics. Gen11 graphics is expected to also feature an advanced media encoder and decoder, supporting 4K video streams and 8K content creation in constrained power envelopes. Gen11 will also feature Intel® Adaptive Sync technology enabling smooth frame rates for gaming.

    Intel also reaffirmed its plan to introduce a discrete graphics processor by 2020.

    (comments?)

    Posted on Wednesday, December 12 2018 @ 15:46:24 CET by Thomas De Maesschalck
    INTC logo
    The other big news from the Intel Architecture Day is the announcement of Sunny Cove. It appears Intel has dumped the 10nm Cannon Lake in favor of the 10nm Sunny Cove. Compared with Skylake, which is still the base of the current Coffee Lake Refresh, the Sunny Cove architecture will be able to execute more instructions in parallel. It has more cache, enhanced branch prediction, more execution units (ten per core vs eight with Skylake), and new instruction sets for machine learning and encryption.
    New Sunny Cove CPU Architecture: Intel introduced Sunny Cove, Intel's next-generation CPU microarchitecture designed to increase performance per clock and power efficiency for general purpose computing tasks, and includes new features to accelerate special purpose computing tasks like AI and cryptography. Sunny Cove will be the basis for Intel's next-generation server (Intel® Xeon®) and client (Intel® Core™) processors later next year. Sunny Cove features include:

  • Enhanced microarchitecture to execute more operations in parallel.
  • New algorithms to reduce latency.
  • Increased size of key buffers and caches to optimize data-centric workloads.
  • Architectural extensions for specific use cases and algorithms. For example, new performance-boosting instructions for cryptography, such as vector AES and SHA-NI, and other critical use cases like compression and decompression.

    Sunny Cove enables reduced latency and high throughput, as well as offers much greater parallelism that is expected to improve experiences from gaming to media to data-centric applications.

  • (comments?)

    Posted on Wednesday, December 12 2018 @ 15:39:47 CET by Thomas De Maesschalck
    INTC logo
    Quite a lot of news from Intel's Architecture Day, we'll cover it in small bits. First up is the news about "Foveros", a new 3D packaging technology for the stacking of logic chips. This builds upon the EMIB 2D packaging technology, and enables logic-on-logic integration. The first product with Foveros 3D stacking is expected in the second half of 2019. Intel says this will be a product that combines a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. The promise of this product is to enable "world-class performance and power efficiency in a small form factor." At the event, Intel showed a 12mm x 12mm SoC with two Core cores, two Atom cores, DRAM, and I/O.
    Industry-First 3D Stacking of Logic Chips: Intel demonstrated a new 3D packaging technology, called "Foveros," which for the first time brings the benefits of 3D stacking to enable logic-on-logic integration.

    Foveros paves the way for devices and systems combining high-performance, high-density and low-power silicon process technologies. Foveros is expected to extend die stacking beyond traditional passive interposers and stacked memory to high-performance logic, such as CPU, graphics and AI processors for the first time.

    The technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller "chiplets," where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top.

    Intel expects to launch a range of products using Foveros beginning in the second half of 2019. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. It will enable the combination of world-class performance and power efficiency in a small form factor.

    Foveros is the next leap forward following Intel's breakthrough Embedded Multi-die Interconnect Bridge (EMIB) 2D packaging technology, introduced in 2018.

    (comments?)

    Posted on Wednesday, December 12 2018 @ 12:34:31 CET by Thomas De Maesschalck
    SpaceX and NASA decided to delay the launch of the unmanned Crewed Dragon test flight by ten days. The new date of the demonstration mission is January 17th. A second, crewed test flight is scheduled for sometime in April 2019, and if everything goes well the first regular flight may occur in September 2019.
    NASA frames this as an “adjustment” rather than a delay. Although, delays are nothing new in spaceflight. It’s a high-stakes mission even if there won’t be any passengers aboard. Even a small error could result in a significant setback as NASA and SpaceX scramble to identify and fix the issue. A minor fuel leak on Boeing’s CST-100 Starliner crew capsule several months ago contributed to a multi-month delay in its testing schedule.
    SpaceX Crewed Dragon

    Via: ExtremeTech
    (comments?)

    Posted on Wednesday, December 12 2018 @ 12:25:12 CET by Thomas De Maesschalck
    Intel logo
    One of the things Intel is revealing at today's 2018 Architecture Day is a new platform codenamed "Sunnycove". No official word yet about what Sunnycove is, but it's believed to be another derivative of the Skylake core instead of a completely new design.

    The chip giant has a working system on display and promises Sunnycove offers "up to 75 percent" higher 7-Zip performance. Sunnycove has new ISA capabilities including vector-AES + SHA-NI, and is capable of accelerating most common cryptographic algorithms.

    No further details yet.

    Intel Sunnycove

    Via: TPU
    (comments?)

    Posted on Wednesday, December 12 2018 @ 12:20:43 CET by Thomas De Maesschalck
    Intel logo
    EE Times reports both Intel and Samsung revealed embedded MRAM technologies at last week's 64th International Electron Devices Meeting (IEDM) in San Francisco. Interestingly, Intel described its STT-MRAM as production ready and multiple sources told the site that Intel is already using it in commercial products:
    Intel (Santa Clara, California) described the key features of spin-transfer torque (STT)-MRAM–based non-volatile memory into its 22FFL process, calling it “the first FinFET-based MRAM technology.” Describing the technology as “production-ready,” Intel did not name any foundry customers for the process, but multiple sources said that it is already being used in products now shipping.

    Samsung (Seoul), meanwhile, described STT — MRAM in a 28-nm FDSOI platform. STT-MRAM is regarded as the best MRAM technology in terms of scalability, shape dependence, and magnetic scalability.
    MRAM is sort of a replacement for both DRAM and NAND flash memory, and it's also an alternative for embedded SRAM thanks to better read/write times, high endurance, and strong data retention. MRAM is more scalable than SRAM, which isn't shrinking with the rest of the process with smaller process technology.
    (comments?)

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