Intel admits 10nm is delayed, confirms 14nm Kaby Lake and possible EUV at 7nm

We briefly covered Intel's earnings report yesterday evening but as usual some more golden nuggets were shared during the conference call with financial analysts. CEO Brian Krzanich confirmed the rumors that have been going around for a couple of weeks now, the 10nm node is delayed due to the technical challenges of shrinking transistors ever smaller. As such, Intel has seen its node transition lengthen to 2.5 years instead of the two-year cycle we've seen with past product introductions.

What this means is that the 10nm Cannonlake processors are delayed to the second half of 2017. To address the gap on the roadmap, Intel will launch a third 14nm chip called Kaby Lake - this model will be based on the Skylake architecture but promises "key performance enhancements".

The last thing I'd like to share with you is an update related to our 10-nanometer technology transition. Just last quarter we celebrated the 50th anniversary of Moore's Law. In 1965, when Gordon's paper was first published, he predicted a doubling of transistor density every year for at least the next 10 years. His prediction proved to be right. And in fact, in 1975, looking ahead to the next 10 years, he updated his estimate to a doubling every 24 months. These transitions are a natural part of the history of Moore's Law and are a by-product of the technical challenges of shrinking transistors while ensuring they can be manufactured in high volume.

As node transitions lengthened, we adapted our approach to the Tick-Tock method, which gave us a second product on each node. This strategy created better products for our customers and a competitive advantage for Intel. It also disproved the death of Moore's Law predictions many times over. The last two technology transitions have signaled that our cadence today is closer to 2.5 years than two.

To address this cadence, in the second half of 2016 we plan to introduce a third 14-nanometer product, code named Kaby Lake, built on the foundations of the Skylake micro-architecture but with key performance enhancements. Then in the second half of 2017, we expect to launch our first 10-nanometer product, code named Cannonlake. We expect that this addition to the roadmap will deliver new features and improved performance and pave the way for a smooth transition to 10-nanometers.

As we move forward, we are focused on innovation and execution. We continue to be confident in our strategy to drive growth.

The announcement also means Intel is no longer following its famous Tick-Tock cycle, it now looks more like a Tick-Tock-Tock model. This is one of the reasons why Intel just lowered its capex budget for 2015 by another billion, by staying longer on 14nm and delaying some of the purchases on 10nm due to the new 2.5 years cadence expenditures are going down. CFO Stacy Smith also explained in the conference call that Intel's 14nm fabs are getting more efficient and that the chip giant took advantage of some of the unit weakness they saw to bring down the capacity in 22nm fabs and rolled it forward to 14nm.

Responding to a question about what exactly is going on with the 10nm push-out, CEO Brian Krzanich clarified the lithography is continuing to get more difficult and also shared some comments about EUV. Krzanich hinted the 2.5 year cadence is not set in stone, he promised Intel is striving to get back to a two year cycle:

No, I'd call it similar to what happened on 14-nanometer. Remember, on all of these technologies, each one has its own recipe of complexity and difficulty, 14-nanometer to 10-nanometer same thing that happened from 22-nanometer to 14-nanometer. The lithography is continuing to get more difficult as you try and scale and the number of multi-pattern steps you have to do is increasing. This is the longest period of time without a lithography node change. So we're assuming 10-nanometers does not have EUV [Extreme Ultra-Violet] for our technology; that combined with just the other material science changes you do with the new technology.

And then you look at the pattern we've been having with the same kind of sets of conditions, which was the 22-nanometer technology and the 14-nanometer technology. And we said those took about 2.5 years. And the feedback from our customers that said, look, we really want you to be predictable. That's as important as getting to that leading edge. We chose to actually just go ahead and insert; since nothing else had changed, insert this third wave.

When we go from 10-nanometer to 7-nanometer, it will be another set of parameters that we'll reevaluate this. We'll always strive to get back to two years. And we'll take a look at what's the maturity of EUV, what's the maturity of the material science changes that are occurring, what's the complexity of the product roadmap that we're adding, and make that adjustment out in the future here. So, we took a snapshot of the 14-nanometer to 10-nanometer transition. We looked at the history, and we said let's be very predictable and do the best thing for shareholders and for our partners and customers.

Asked about what this means for Intel's leadership position in the process node space as everyone seems to be getting to 10nm at the same time in 2017, Krzanich responded he does not expect Intel's lead to change dramatically:

I think first, John, I'll just say, we believe, even with this 2017, our lead in Moore's Law will not change dramatically. We believe we'll continue to lead with roughly the same leadership position that we have today. We base that on, one, what really counts when I talk about 2017, that's not samples, that's not small volume. That's converting over to Cannonlake and producing a large percentage of our CPUs in volume in the second half of 2017. So there's a bit of definition. When we say second half of 2017 we're talking about millions of units and large volumes.

And then as you said, there's this definitional difference, right. This will be now our third generation of FinFETs by then. It will have several other transistor enhancements. And we believe if you take a look at the scaling, it will be quite strong relative to the normal scaling parameters that occur with the Moore's Law transition. I'm not going give you the exact numbers right now. But we think if you combine all those together, our leadership position doesn't change, even with this date.

CFO Stacy Smith answered a question about the long-term capex implications, he replied it's hard to make estimates for this as each process technology node has its own "personality". He said more will be revealed at Intel's investor meeting and added that Intel is trying to bring in the long-delayed EUV lithography at 7nm.

I'm going to punt on that one, C.J., until the investor meeting and we'll talk a bit more. And one of the reasons that's hard is, as Brian talked about, each one of these process technology transitions has its own personality. At 7-nanometer, we're trying to bring in EUV. Depending on the health of that, we could be at two years, we could be at 2.5 years, and that will change this answer. So we'll give more insight into this in the Q4 investor meeting.

Going further in-depth Smith mentioned Intel is still uncertain about the cadence of its 7nm process. If it's two years we can expect two waves of products as usual but if it slips further it's going to be three waves like on 14nm.

And just as I think about this and simplify it in my head, the way I think about it is if a process node were on a two-year cadence, two waves of products is the thing that delivers the best value to the customers and then we quickly get to the next node. When the process node transition shifts out to be longer than that, then that third wave of products gives us another opportunity to deliver features to the customer. And so the uncertainty you're hearing isn't whether this is a good model or not. The uncertainty is 7-nanometer, there's still enough open questions that we don't know exactly the cadence.

Transcript courtesy of Seeking Alpha