Unlike the more popular ARM and x86 variants, RISC-V is designed to be used universally, from the smallest embedded devices to industrial-scale cloud computers. The appeal of RISC-V is that it's much smaller than the commercially available ISAs, it requires more design work from the chip vendor but allows for a "clean slate" approach.
Barron's has some more details about RISC-V over here.
[Chip veteran Rick] O’Connor’s sales pitch for RISC-V is that it is “far smaller than other commercial ISAs,” which can produce economic benefits when making chips with it; it is a “clean slate” approach, which has carefully through through things such as what parts should be “user space,” in a chip, and what “privileged,” which might help avoid some really bad security issues like the recent “Spectre” bugs faced by Intel, and it is designed to be extended as chips need to gain new capabilities.RISC-V has been around since 2010 but the big news is that it's slowly gaining traction outside the academic world. Google's TPU is based on RISC-V work and several other tech giants are also adopting this new ISA for various projects.
As O’Connor explained in a single slide, most computing devices today are in a sense trapped in some “proprietary” instruction set, such as Intel’s, as he outlined in the slide at the top of this post. RISC-V suggests a certain lessening of the dominance of individual vendor designs, he implied.
NVIDIA for example will use RISC-V for the Falcon CPU that it puts into its GPUs. This is a proprietary microcontroller that's been part of NVIDIA GPUs for well over a decade. The new generation will be based on the RISC-V ISA and promises better performance and some new capabilities. Another company that is adopting RISC-V is Western Digital, they will use the ISA for all their future storage disk processor chips.