TSMC taped out first 7nm chip with partial EUV

TSMC announced it taped out its first customer chip in a N7+ node that can use extreme ultraviolet (EUV) on up to four layers. This makes TSMC the first in the foundry industry to achieve that feat. Samsung is currently ramping a 7nm node using EUV, Intel isn't expected to adopt the new lithography technique anytime soon, and GlobalFoundries shelved its plans for 7nm and EUV.

EUV risk production on TSMC's N5 node will start in April 2019, that process will use EUV on up to 14 layers.

Based on tests with ARM A72 cores, TSMC says the N7+ node delivers 20 percent better density and a 6-12 percent enhancement in power efficiency. The N5 node will deliver 14.7 to 17.7 speed gains and a 1.8-1.86 area shrink.

Chip designs for the N5 node can start today, although most EDA tools won’t hit a 0.9-version readiness until November. Many of TSMC’s foundation IP blocks are ready for N5, but some including PCIe Gen 4, USB 3.1 may not be ready until June.

The N7+ node sports a tighter metal pitch and includes a single-fin library that can help lower dynamic power. It will be available in a version for automotive designs by April. N7+ offers “nearly the same analog performance as N7,” said Cliff Hou, vice president of technology development at TSMC.

One big problem is that chip designs for these nodes are getting exponentially more expensive. It's believed that the total costs for an N5 design will come in at $200 million to $250 million, up from $150 million for a 7nm chip today. Basically, more and more chip designers will stick with older nodes as bleeding-edge tech is becoming too expensive. More details about TSMC's latest process tech can be read at EE Times.