The reason for this pipeline/ROP configuration is that ROPs are often left idle while work in the shader pipelines are taking more than one cycle, thus rarely would all twelve output units required at any one time, especially with the kind of work being asked of a mid-range board. If you're looking for a real-world comparison, think of queuing to enter a football stadium that has twelve turnstiles, but only eight entrances to the actual seating beyond that..



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