At present JEDEC is discussing LPDDR4 standard that includes 3200Mb/s data rate (3.2GHz effective clock-speed), 350mVpp max signaling with configurable termination using low-voltage swing terminated logic as well as 1.1V voltage. In addition, data bus inversion has been added to improve signal integrity. Perhaps, one of the main changes of LPDDR4 over previous-generation standards is that LPDDR4 memory die will architecturally be two-channel x16 DRAM.
"The challenge is how to achieve that energy reduction at 3200Mb/s, and the sub-committee had to look at architectural, signaling and voltage changes. […] The objective is to improve timing closure, as well as reducing internal DRAM die power,” said Hung Vuong, chairman of JEDEC's JC-42.6 subcommittee for low power memories, in a conversation with EETimes-India.
LPDDR4 standard to arrive in 2014
Posted on Thursday, Dec 19 2013 @ 16:17 CET by Thomas De Maesschalck
X-bit Labs reports the LPDDR4 specification is on track to be finalized in 2014. The new standard promises up to double the bandwidth performance and 50% lower power consumption but it's unlikely to be adopted rapidly due to the traditionally high initial price and limited production. At first, it will primarily be high-end mobile devices that will jump on the LPDDR4 bandwagon.