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Intel Z270 chipset block diagram leaks, confirms more PCIe lanes

Posted on Wednesday, December 21 2016 @ 14:39:39 CET by

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Earlier this week eTeknix voiced its displeasure over Intel's EMEA sampling policy by sourcing Kaby Lake chips from an alternative source and published two reviews well before the official NDA expiry. Now the site leaks a block diagram that shows off the feature set of the new Intel Z270 chipset.

LGA1151 motherboards based on this new chipset are expected at CES 2017 in January, they are compatible with Skylake and feature a DDR4 memory bump to maximum 2400MHz. The biggest change perhaps is the increase in the number of PCI Express lanes:
The new chipset appears to be largely the same with only 1 major difference. The PCIe lane count gets bumped up by 4 more lanes to 24 PCIe 3.0 lanes in total. For everything else, it is much the same with the same number of 10 USB 3.0 and 14 2.0 ports with 6 SATA ports for storage. Given the backwards compatibility with Skylake CPUs, I guess Intel couldn’t go too crazy with the changes. One caveat for parts like the Ethernet connection, while the name might be the same, Intel could have changed the features up and added improvements on a low level.
For desktop users, Kaby Lake is another incremental update that won't generate a lot of excitement. There is a bit of a performance enhancement but this is primarily due to higher frequencies and an improved Turbo. Other than this, there are some good gains in the integrated graphics department and the chips overclock well. But on a clock-for-clock basis, there's pretty much no improvement versus Skylake.

The big thing to look forward to is the new Zen architecture from AMD, it will be interesting to see how well Ryzen stacks up with Kaby Lake.




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