Posted on Friday, April 27 2018 @ 10:22 CEST by Thomas De Maesschalck
He also said part of the reason why 10nm is so hard for Intel is because this is the last node that doesn't use EUV, which has an impact on the amount of multi-patterning and the effect of that on defects.
As you may know, EUV is the next big step in lithography. The current immersion lithography is running against the limits of what is physically possible, but the road to EUV has been long and hard. A couple of years ago, many industry experts feared EUV would never hit maturity, but now it looks like chip makers will be able to use EUV in the near future as Dutch semiconductor equipment maker ASML has made a lot of progress. Still, it's not as if EUV will make smaller nodes a walk through the park.
Krzanich says the current roadmap calls for EUV on the 7nm node and he reiterated the plan for heterogeneous techniques. Basically, Intel is adopting new packaging techniques that will enable multiple process nodes to be used on a piece of silicon. High-performance elements will be made on 7nm for instance, while parts that don't benefit from the latest process technology could be made on 14nm or even 22nm. Here's Krzanich's full explanation about the 10nm issues:
Sure, so the issues around 10-nanometer, I'm trying to lay that flat out without getting too deep into the technology. But this is the last technology that doesn't incorporate EUV. And what you also need to understand is that we took very aggressive goals at 10 nanometers. So if you talk about the scaling factor or think about it as the multiple at which you shrink a feature, we took a target of 2.7. So you took any feature and run over 2.7 is the dimensional shrink that you did to this device. For example, on 14-nanometer, we took a target of 2.4, so you're almost 10% more aggressive on 10 nanometers.
And if you look at what is the industry standard, what the foundries and other players are typically doing, they're typically in that 1.5 to 2.0 range. So there, we're maybe 20% more aggressive. So it's very aggressive goals to hit our cost targets and where we want the technology to be. And that combined with the end of life of the immersion scanner before we hit EUV has just created something that's a little bit more difficult.
So that's why I have the confidence that this is not something we're shipping. The transistors work. We know the performance is in line. So it's really just about getting the defects and the costs in line to where we want.
As far as what does that imply for future technologies, we made a lot of changes at 7 nanometers. 7-nanometer currently is the first technology forecasted to implement EUV, so that immediately makes the lithography system different. We're going back to a more standard, for us, compaction number of 2.4, so that makes it a little bit easier. We think we bit off a little too much in this case. And it may not seem like a lot, but 10% can make a lot of difference in this kind of a world.
And thirdly, we are using some very unique packaging technologies and such that allow us. At 7 nanometers and beyond, we're really moving to a world where you're not going to look at any piece of silicon as being a single node. You're going to use what we're going to call heterogeneous techniques that allow us to use silicon for multiple nodes. So you may use cores from 7 nanometers and IP from 14 nanometers and even as far back as 22 nanometers for the parts that don't need the high performance. And we're able to put those together and make them perform and behave like a single piece of silicon in the package. So really 7 nanometers is quite a bit different, and so I think as a result, we don't expect to see these kinds of impacts on 7 nanometers.
