Online reports suggest that VIA will launch its x86-compatible Esther processor in Q4 of this year. This schip, that will sell under the name C7, will take the family beyond 2GHz.
To date, VIA has said that the chips will operate using an 800MHz frontside bus clock. It will sport the fourth generation of VIA's PowerSaver energy conservation technology and provide RSA encryption (with Montgomery Multiplier support) and Secure Hashing (SHA-1 and SHA-256) acceleration to the hardwired security-oriented functionality the current C3 chips already provide. C7 will also support Intel's SSE 2 and 3 multimedia-oriented instruction sets and the 'no-execute bit' support. It will feature a larger L2 cache than the C3's 64KB.