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“We will support the disabling of one core in BIOS in a future BIOS rev.,” said Daniel Snyder, a spokesman for Intel Corp., when asked about the background of the technology. This means that once one core is disabled, the whole 2MB or 4MB cache reservoir on microprocessors that have shared level-two (L2) cache will be usable by one processing engine, which should boost performance in applications that cannot take advantage of two executing cores.

It is highly-likely that the feature will only work on the upcoming Core 2 processors code-named Conroe, which have shared L2 cache between its cores. It is also likely that the capability will allow quad-core chips to act like two dual-core processors in situations when four processing engines cannot be used efficiently.