Rambus says it will offer its 65nm PCI Express Gen2 PHY solution at TSMC by mid-2007.
Showcased last month at the Intel Developer Forum (IDF) in San Francisco, the Rambus PCIe Gen2 solution is currently based on a preliminary version of the PCIe 2.0 standard, which has already reached the 0.9 revision stage. The final specification is expected to be approved and published by the PCI Special Interest Group (PCI-SIG) by the end of this year.
Rambus is not a member of the PCI-SIG, and it has no plans to join the organization in the near future, according to company CEO Harold Hughes.
Scaling the transfer rate from the current 2.5 gigatransfers per second (GT/s) to 5GT/s, the PCIe 2.0 standard also offers new challenges to IC designers due to the shorter clock cycle, Rambus pointed out. Promoting its PCIe 2.0 PHY solution in Taiwan to help address the challenges, Rambus is primarily focused on chipset and GPU (graphics processing unit) vendors, the company said.