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Toshiba, Sony and NEC unveil 45nm platform technology

Posted on Friday, December 15 2006 @ 11:22:24 CET by

Toshiba Corporation, Sony Corporation and NEC Electronics Corporation today announced the successful co-development of an LSI mass production platform for next-generation 45 nanometer (nm) process technology. The new platform integrates elemental breakthroughs with cutting-edge technologies to achieve a highly efficient process for production of high performance system LSI. This technology was unveiled on December 13 (US Pacific Standard Time) at Session 27.2 of the 2006 International Electron Devices Meeting (IEDM) in San Francisco, CA.

The key elements of the new platform are a fully renovated MOSFET integration scheme, and a hybrid structure with a low dielectric constant (low-k) film that assures high performance and reliability.

The MOSFET integration process applies strained silicon technology to the transistor, utilizing crystal lattice distortion to induce performance-boosting local strain at key locations. Optimization of the strain boosts transistor performance to a level 30% faster than that achieved in the present generation of technology.

Application of a low-k film in the intermediate metal layer of the chip during the back-end process reduces parasitic capacitance and improves circuit performance. The three partners confirmed a dielectric gate film with an effective 15-year lifetime, a span surpassing the average lifetime of a high performance LSI. They also carried out exhaustive tests of the platform and proved a layer yield of over 98% for the challenging back-end process, confirming that the technology achieves the reliability essential for mass production.

In addition, the partners have led the industry in applying immersion lithography technology with an ultra-high numerical aperture (NA) of over 1.0 to formation of the transistor node, achieving a cell with an area of 0.248 micron m2 in an ultra high density SRAM. The new cell is the smallest yet achieved.

The three companies are simultaneously developing two 45nm processes -- the current platform, which is ideal for high performance LSIs, as well as a platform for applications with low power consumption requirements, which is expected to be completed in early 2007.



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