Posted on Tuesday, June 12 2007 @ 17:27 CEST by Thomas De Maesschalck
Some info about Intel's Nehalem processor appeared on
X-bit Labs, they write the chip will feature a three-channel memory controller and a Common Serial Bus (CSI).
In particular, Intel already announced that, among other things, it would be able to scale and configure caches, interconnect controllers as well as memory controllers. Already now Intel can reduce or increase cache sizes for various processors without many problems, whereas Advanced Micro Devices can enable or disable Hyper-Transport links within its processors depending on their positioning (e.g. AMD Opteron processors for multi-processor servers have three HT links, whereas Athlon 64 for 1P machines have only one HT link). But Intel wants to go even further and scale the number of memory controller channels. According to PC Watch web-site, the top Nehalem processor code-named Bloomfield with four cores will have triple-channel DDR3 memory controller, whereas slightly less advanced may have less channels.
Three memory channels supporting PC3-12800 (DDR3 1600MHz) memory would provide approximately 38.4GB/s memory bandwidth, up significantly from about 21.3GB/s memory bandwidth available today. Given that in 2009 Intel plans to release Nehalem processor with built-in graphics core, triple-channel memory controller may help to keep performance in 3D games on relatively high level.
The Intel Nehalem processor is expected in late 2008.
