AMD talks about K9, K10 future innovations

Posted on Saturday, October 18 2003 @ 0:08 CEST by Thomas De Maesschalck

Some info about AMD his upcoming CPU micro-architectural innovations were announced at the Microprocessor Forum 2003. Some of these innovations, they say, will take place in all microprocessor families like x86, SPARC, PowerPC,...

Some innovations in the upcoming AMD K9 and K10 :

Threaded architectures;
Chip level multiprocessing;
Huge scale MP machines;
10GHz operation;
Much higher performance superscalar, out of order CPU core;
Huge caches;
Media/vector processing extensions;
Branch and memory hints;
GHz performance IO;
Security and virtualization;
Static and dynamic power management.

X-bit Labs comments that most of these features aren't new. Multi-threaded architectures are already available (like Intel his Hyper-Threading).

Chip level multiprocessing will take place next year for IBM with their Power5. And in 2005 for AMD, Intel and Sun with dual-core processors. AMD claims that their first dual-core chips will be based on their current K8 serie.

Operation at unbelievable frequencies, huge caches as well as powerful CPU and I/O buses are inevitable parts of performance progress. There are no doubts that AMD K9, AMD K10, AMD K11 in addition to other microprocessors will work at high core-speeds and employ large L1, L2 and possibly L3 caches. Obviously, the K9 will hardly achieve 10GHz, but K10 will surely hit this important milestone. It will be amazing in case after 10GHz we will see 20GHz, 30GHz and so on, just like we witnessed the thorny way from 10MHz to 33MHz in the eighties.

The other innovations like media and vector processing extensions, branch and memory hints, ... are also found in today his processors (Intel his MMX, AMD his 3DNow!). More extensions like these can be expected in the Athlon 64, K9 and K10. Another thing that is sure is that the AMD K9 will support Microsoft his Palladium security.

Source : X-bit Labs

AMD talks about K9, K10 future innovations

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