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Why it is possible that Intel will use the AMD64/x86-64 instruction set

Posted on Monday, October 27 2003 @ 23:02:47 CET by

Kyle from [H]ardOCP has posted a small article today on his website about the whole 64 bit issue. He mentions an important agreement between AMD and Intel, of which I did not know that it officially excisted :

First let me ask you this. Why do current Athlon64s utilize the "SSE2" instruction set? Isn't that technology proprietary to Intel? Of course it is. Then why would Intel allow their intellectual property to be exploited by AMD? The answer is a simple one. Intel "gave" it to AMD.

Much the same way AMD will "give" Intel the AMD64/x86-64 instruction set.

We confirmed with AMD's Damon Muzny several weeks ago that AMD and Intel have an agreement about sharing technology. While we have asked for more details beyond that, none have been given. One thing was certain to us after the conversation, and that was that Intel will have the ability to utilize the x86-64 technology developed by AMD. At what cost exactly is unknown to us.

The real questions are simple. How quickly could Intel implement the X86-64 instruction set? And. Would Intel want to implement the AMD contrived x86-64 instruction set or would they rather use something of their own?
Dan Niles, Lehman Brothers' ace analyst, believes that Intel is going to release a rival to AMD's 64-bit hybrid x86 chip, the Athlon64, in the first half of next year and that it could trash AMD's processor sales.
One thing is for sure, Intel will not be calling it “AMD64” should they decide to utilize the instructions...or would they have to.

UPDATE: I did just finally find a great link from 2001 that summed up the agreement mentioned above.
The companies have signed four patent cross-license agreements since 1976, said John Greenagel, an AMD spokesman. "Anything that we patent they can use, and anything they patent we can use," he said.

The agreement covers patent and certain copyrights, he said. Specific terms of the 10-year agreement remain undisclosed.

Source : [H]ardOCP



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