The PCI Special Interest Group is going to add some extensions to the PCI Express 2.0 specification in June 2008. The new features will boost performance and will allow a smoother integration with accelerators and storage devices.
The enhancements include limited support for cache-coherent transactions as a way to synchronize traffic, particularly between host CPUs and co-processors, a new technique for handling virtual memory and support for multicasting. The SIG hopes to define these features—and perhaps others-- as engineering change notices on top of PCI Express version 2.0 by April, although some items may not be completed until June.
The work "has really come together these past couple of months. Training on the concepts has started to the members to prep them for the [spec] reviews," said one source who asked not to be named.
"It's all incremental advances, but in certain markets they will be significant," said a second source who asked not to be named.
Chip interconnects represent a competitive arena where Intel and archrival Advanced Micro Devices are sparring. Intel is expected to use the enhancements to Express as the main route for third-parties to link to its chip sets and CPUs, competing with versions of HyperTransport used by AMD.
The multicast capability will let a PCI Express switch blast one element of data to multiple end points, saving bandwidth and latency in some applications. The feature will be most useful in systems that use multiple graphics chips or monitors or systems with redundant or mirrored storage capabilities.