Intel has notified its partners about the specifications of its upcoming high-end Alderwood chipset.
One of the things this chipset supports is ofcourse Socket T (socket 775 LGA), another new thing is a new memory controller hub (MCH) backbone which will support DDR2 memory.
The architecutre supports asynchronous and isochronous data, with dedicated internal pipelines, and Intel is touting better electricals with optimised ball out and an extra "bypass" (eek) enabled.
The MCH uses a 1210 flip chip ball grid array, while the different ICHs in the shape of ICH6, ICH6R, ICH6W and ICH6RW use a 609 micro BGA package.
A home grown version of PCI Express, known as the direct media interface (DMI) links the MCH to the IO controller hub, and this is claimed to deliver 2GB/s bandwidth compared to the old and feeble 266MB/s.
Other things that are supported are High Definition Audio, with Dolby up to 7.1, four Serial ATA controllers, an AHCI (Advanced Host Controller Interface) which is claimed to give faster boot times and transfer rates of up to 150MB/s. RAID 0 and RAID 1 is integrated, just as an integrated wireless access point.
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