DV Hardware bringing you the hottest news about processors, graphics cards, Intel, AMD, NVIDIA, hardware and technology!

   Home | News submit | News Archives | Reviews | Articles | Howto's | Advertise
DarkVision Hardware - Daily tech news
October 24, 2016 
Main Menu
News archives

Who's Online
There are currently 87 people online.


Latest Reviews
Zowie P-TF Rough mousepad
Zowie FK mouse
BitFenix Ronin case
Ozone Rage ST headset
Lamptron FC-10 SE fan controller
ZOWIE G-TF Rough mousepad
ROCCAT Isku FX gaming keyboard
Prolimatech Magnetic Pin

Follow us

"Intel to launch Xeons next year with 1066MHz FSB"

Posted on Tuesday, May 25 2004 @ 21:27:54 CEST by

It is said that Intel may have plans to introduce Xeon processors for 2-way applications with a 1066MHz bus next year, and that they are already discussing chipsets with support for a 1066MHz with certain partners.
Later this year Intel is expected to unveil Xeon processors with 1MB L2 cache, Enhanced Memory 64 Technology, 800MHz Quad Pumped Bus as well as appropriate chipsets code-named Lindenhurst (E7320, E7520) and Tumwater (E7525) to support the launch. Next year Intel is likely to commercially unveil Xeon processors with 1066MHz processor system bus with appropriate chipsets code-named Blackford and Greencreek, The Register quotes a presentation from Intel’s Tommy Rydendahl. The timeframe for the new core-logic sets introduction is described as mid-2005 or beyond.

Intel recently canned the successors of Pentium 4 and Xeon processors code-named Tejas and Jayhawk in favour of dual-core chips. Nevertheless, the company added Pentium 4 “Prescott 2M” and Xeon “Irwindale” processors into the lineup, according to various reports. The Prescott 2M is projected to have 2MB L2 cache and utilize 1066MHz PSB in addition to some other enhancements, the Irwindale is also anticipated to feature 2MB L2, but to feature 800MHz Quad Pumped Bus.

It is not clear whether Intel plans to enter dual-core processors with 1066MHz processor system bus or revamp some higher-end Xeon “Irwindale” chips to support faster QPB bin.
The nex Pentium 4's with 2MB cache are planned to be available in Q4 2004, and the Irwandale chips are projected for launch in Q1 2005.

Source: X-bit Labs



DV Hardware - Privacy statement
All logos and trademarks are property of their respective owner.
The comments are property of their posters, all the rest © 2002-2016 DM Media Group bvba