Posted on Tuesday, August 19 2008 @ 0:44 CEST by Thomas De Maesschalck
The HyperTransport Consortium rolled out version 3.1 of its specification. This update increases the maximum clockspeed from 2.6GHz to 3.2GHz which results in a bandwidth of 51.6GB/s - up from 41.6GB/s.
HyperTransport is a high-bandwidth, point-to-point interconnect standard that provides the lowest latency for chip-to-chip, board-to-board and chassis-to-chassis links. The HyperTransport 3.1 specification defines three new clock rate steps of 2.8 GHz, 3.0 GHz and 3.2 GHz. This increase in clock speed delivers a 23 percent increase in aggregate bandwidth.
"It is significant that the HyperTransport Consortium has proven its ability to further consolidate interconnect performance leadership with the release of the HyperTransport 3.1 specification," said Jag Bolaria, senior analyst, The Linley Group. "The standard has empowered millions of high-performance products on the market today, proving the stability and robustness of the technology. The move to 3.2 GHz is the next natural progression."
The HyperTransport Consortium also announced a new bus interconnection specification called HTX3. This specification allows graphics cards (and other add-in board cards) to be linked to the CPU using the same interface that links CPUs to memory and could potentially replace PCI Express. HTX3 is based on HyperTransport 3.0 and offers a bandwidth of 41.6GB/s.
