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Intel's dual-core Montecito planned for Q4 2005
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Posted on Monday, January 24 2005 @ 19:12:51 CET by Thomas De Maesschalck |
Intel continues to keep its nose to the grindstone on its re-positioned Itanium microprocessor, with a number of introductions of upgrades slated for this year.
The chip company will introduce an Itanium 2 with 9MB of cache in the third quarter and using the 667MHz front side bus (FSB), according to recent roadmaps seen by the INQ.
More info at The Inquirer
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