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Based on innovations from Rambus’ groundbreaking Mobile Memory Initiative introduced last year, Mobile XDR memory offers a high-bandwidth, low-power memory architecture to enable devices that exceed the power and performance targets for next-generation mobile products.

“Future mobile applications demand far higher performance and longer battery life than today’s mobile products can achieve,” said Sharon Holt, senior vice president of Licensing and Marketing at Rambus. “Mobile XDR memory provides the ideal solution for designers to offer leading-edge mobile content in a dramatically lower power and cost-effective manner. Uniquely, the Mobile XDR architecture delivers these benefits in SoC and DRAM devices that can be built with current manufacturing infrastructure reducing both risk and time-to-market.”

The Mobile XDR memory architecture will enable future mobile memory platforms which can achieve throughputs of up to 4.3Gbps per pin with unequaled power efficiency. With this breakthrough performance, SoC platforms can achieve over 17GB/s of memory bandwidth from a single Mobile XDR DRAM device while extending the battery life of many mobile products by more than 30 minutes, when operating under the most power-hungry usage profiles.

The Mobile XDR architecture enables significant cost savings for SoC chips by offering pin-count reduction and a smaller interface. Power reduction is achieved through an aggressive decrease in active power coupled with fast transition times to power-saving modes. This enables system designers to minimize memory subsystem power to increase battery life across a wide range of applications from simple voice transmission to demanding multimedia such as stereoscopic 3D HD video.

Mobile XDR memory architecture uses key innovations from Rambus’ Mobile Memory Initiative:

• Very Low-Swing Differential Signaling (VLSD): a bi-directional, ground-referenced, differential signaling technology which offers a high-performance, low-power and cost-effective solution for applications requiring extraordinary bandwidth and superior power efficiency.

• FlexClocking™ Architecture: utilizes asymmetric partitioning and places critical calibration and timing circuitry in the SoC interface, greatly simplifying the design of the DRAM interface.

• Advanced Power State Management (APSM): Reduces memory system power and provides ultra-fast transition times between various low-power and active operating modes.

In addition, Rambus’ FlexPhase™ and Microthreading technologies help enable the superior power efficiency of the Mobile XDR architecture.

Key components of the Mobile XDR memory architecture include Mobile XDR DRAM, Mobile XDR memory controller PHY (MIO), and the Mobile XDR memory controller (MXC). The Mobile XDR memory architecture is currently available for licensing. For additional information, please visit www.rambus.com/mobile.