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AMD Orochi chip (which is a universal server and client design that will power Valencia, Zambezi and possibly other implementations of first-gen Bulldozer family) will have 8MB unified level-three cache, according to a document seen by X-bit labs. Since eight-core Orochi features four dual-core Bulldozer modules, each of which is believed to have 2MB of shared level-two cache, the whole chip will pack in whopping 16MB of SRAM, a 77% increase from the current six-core microprocessors that have 9MB of cache in total.

Large L2 caches will help AMD's next-generation microprocessors to ensure higher performance in single-threaded applications compared to today's multi-core chips that only have 512KB of L2, whereas massive L3 cache will maximize memory bandwidth. In both cases this will bring notable performance gains compared to today's Stars/Greyhound architecture.