 |
|
Who's Online
|
There are currently 211 people and 0 DV-member(s) online.
|
|
|
|
|
RSS
|
 |
|
|
|
| |
AMD copies Intel tick-tock model in a different way
| |
Posted on Thursday, January 26 2012 @ 22:41:11 CET by Thomas De Maesschalck |
X-bit Labs reports AMD has quietly adopted Intel's Tick-Tock model. Under AMD's new strategy, Fusion APUs with a "reduced" or "early" micro-architectural feature-set will arrive first, while "full" feature-set CPUs will follow later. Adopting a tick-tock like model will hopefully enable AMD to reduce time-to-market of its new products and decrease the odds of running into severe problems.
AMD wants APUs to be released earlier than fully-fledged CPUs since they are aimed at broader segment of the market. Therefore, x86 cores of Fusion chips will sport "reduced" next-generation micro-architecture (and will fully support previous-gen features and capabilities) in order to cut their development time and reduce their die size. CPUs will come to market several months after APUs and will feature more advanced x86 cores that will support more new instructions and therefore will offer better x86 performance.
For example, only fully-fledged "late" Piledriver inside Viperfish (code-name of next-gen server/desktop die design, the successor of Orochi that powers FX and Opteron chips) will be able to execute numerous new instructions as well as will receive instructions per clock (IPC) increase. Even though reduced "early" Piledriver inside code-named Trinity APUs will be more advanced than the original Bulldozer, the x86 cores are projected to be slightly less efficient than those of the full Piledriver.
|
| |
|
|
| | The comments are owned by the poster. We aren't responsible for their content. |
|
|
|
|
