As you move towards smaller process nodes it becomes harder and harder to continue scaling, but Intel's Mark Bohr believes there's no end to semiconductor CMOS scaling for at least a decade.
Full details at EE Times, the site notes that Bohr was skeptical about 3D chip stacking, and that he noted that multi-chip packages are already in wide use and appear to be far more cost-effective than 3D chip stacking.
"I don't see the end of Moore's Law for at least 10 years," Bohr said. He added that he believes Intel will continue to employ its "tick tock" model—where the company introduces a new architecture one year and follows with a move to a new process node the next—for the foreseeable future.
Responding to an audience question during a Q&A with a group of Intel Fellows at IDF, Bohr said he doesn't accept the conventional wisdom that CMOS scaling must eventually hit a wall. But he added that scaling probably will run out of steam at some point.
Responding to another question at the same Q+A, Bohr said Intel is studying ways to implement 3-D chip stacking in package, but sounded skeptical about the chances of the firm implementing it. "Having the technology and having a cost effective solution are two different things," Bohr said. "We can do 3-D chip stacking, but I think the added cost is still a bottleneck."
