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Hybrid Memory Cube Consortium has presented their second-generation specification. The new spec promises to double the bandwidth of the three-dimensional memory technology to 30Gbps. Hybrid Memory Cube chips stack memory wafers to create a 3D cube, the technology promises much faster performance than DDR3, while having a more compact footprint and a power draw that's up to 70 percent lower than a traditional planar memory design.
Now, the Consortium has announced the second generation of the HMC specification, which further increases the throughput. According to figures released by Micron, co-founder of the Consortium, the short-reach performance has been boosted from a previous peak of 15Gb/s to 30Gb/s - a doubling which will significantly increase overall performance of the parts. 'The HMC Gen2 specification doubles the interface data rate, which enables system designers to more easily realize performance gains with next-generation 20nm and 14nm FPGAs and SoCs,' explained Patrick Dorsey, senior director of product marketing at HMC Consortium member and FPGA specialsit Altera. 'Our early start in delivering evaluation boards and the demonstrated interoperability between Hybrid Memory Cube devices and FPGAs enables customers to immediately start evaluating and developing HMC-based, high-performance systems.'