Posted on Thursday, September 29 2005 @ 2:28 CEST by Thomas De Maesschalck
The Inquirer has some bad news about about Intel's Montecito and Montvale. They report these chips will have a clockspeed of at least 100MHz lower than expected and that it will arrive later than planned with less features..
The current woeful state of affairs seems to be centred around power management, the vaunted Foxton looks like it is the root cause of the problems in a big big way, and it may well be the first bit on the chopping block.
But let's start with the good news, there really will be a 2.0GHz 24MB 800MHz FSB version. That is it. The bad news starts with when. As it stands right now, the launch is divided into two phases, and those are a bit fluid, and may change. I will give you the rosy outlook.
Phase one centres around one of two steppings, a C1 or Dx, depending on the state of C1 and whether it necessitates a Dx stepping. The current stepping C0 has taped out with 'sub-optimal validation', in 1337-speak, it means it was rushed out the door and buggy. Samples are expected to reach customers in about two months, and that is when the system level work can really begin.
Read on over
here.
