Elpida recently announced the development of new high-speed, low-power circuit technologies for DDR3 SDRAM in a paper presented at the International Solid State Circuits Conference (ISSCC). The new technologies consist of a transfer circuit that realizes high-speed access time (data readout time), and a data readout timing generator that enables stable high-speed data transfer rate in the DRAM's output block. Using the new technologies, Elpida produced a 512 Megabit DDR3 SDRAM with a column access time of 8.75 ns and data transfer rate of 1.6 Gigabits per second (Gbps). This is an ultra-fast next-generation DRAM for the high-end server and computing markets.
With the dramatic rise in processor clock frequencies, DRAM must deliver an even faster operating performance without sacrificing power efficiency. Following the standardization of high-speed DDR1 and DDR2 SDRAM, the DDR3 SDRAM specification is now in the process of being standardized. DDR3 effectively doubles the performance of the DDR2 architecture and is expected to become the next-generation DRAM that realizes high-speed data readout and high-speed data transfer while operating at a mere 1.5 V.
In developing next-generation 512 Megabit DDR3 SDRAM, Elpida wanted to provide high-end DRAM customers with circuit technologies that would deliver a faster access time and a faster data transfer rate than any other product. Elpida found that the data readout speed could be increased by blanket-reading data from the DRAM's memory array and transferring that data to the output circuit using time division, thus cutting down on the number of data signal lines required and reducing the parasitic capacitance. The company also devised a technology that would enable high-speed data transfer by developing counters that could control generation of the data readout timing on a clock with double the cycle time of DDR2 while still providing enough operating margin.