Posted on Wednesday, March 08 2006 @ 22:29 CET by Thomas De Maesschalck
Lots of stuff was presented at the IDF yesterday, including the Merom processor.
We'll dive into the architecture of Merom tomorrow, but until then here's what we do know. Merom, like Conroe, features a 14-stage integer pipeline, up from the 12-stages in Yonah. Merom also happens to be a wider 4-issue core, meaning it can fetch, decode, execute and retire up to four instructions per clock (compared to 3 in Yonah).
We mentioned earlier today that Intel's new Core micro-architecture would support the fusion of x86 instructions as well as micro-ops, which should increase the efficiency of the CPU as well as help to reduce power.
You can check out the full coverage at
AnandTech. It also covers the mobile 2006-2007 roadmap, some interesting concept notebooks, Robson, WiMAX and the UMPC.
