Posted on Friday, September 22 2006 @ 15:55 CEST by Thomas De Maesschalck
The Reg
claims Intel will announce it will open its socket specifications next week at the Intel Developer Forum, just like AMD did with its
Torrenza initiative.
Multiple sources have confirmed that Intel, for the first time, will open up its chip architecture to partners. One element of the companies agenda centers around releasing extensions for PCI Express and other buses that will allow other companies to develop co-processors for Xeon-based motherboards. In addition, Intel has been trying to woo partners to build co-processors for its upcoming Common System Interface (CSI).
Last month, Intel held a CSI partner day of sorts in Portland. Close to 30 companies attended the event at which Intel laid out vague plans for CSI. The technology, due out in 2008, is a response to AMD's Hypertransport technology that allows processors and other components to communicate. When CSI arrives, Intel is also expected to move to processor designs with integrated memory controllers as AMD has done for years.
So far, AMD has allowed various companies to make accelerators, networking products and FPGAs that tap into Hypertransport. This has created a young but fertile market for add-on gear that can add some processing muscle to Opteron-based servers. On the FPGA front, for example, companies like Cray plan to create FPGA/Opteron combo systems that crank through high performance computing code.
