Since Kentsfield appears to have two separate L2 caches, shared separately by each pair of processors, bus bandwidth consequently increases, the makers said. In contrast, Yorkfield will have one L2 cache shared directly by each pair of chips, enabling more efficient quad-core operation, with less FSB bandwidth, the makers noted.
Intel's Yorkfield will be paired with the next-generation Bearlake chipset family, which will support a 1333MHz FSB and a PCI Express 2.0 interface, according to the makers. The first Yorkfield-based systems, which will utilize the Bearlake X chipset and DDR3-1333 memory, will target the high-end gaming market, said the makers.
Intel Yorkfield 45nm quad-core processor planned for Q3 2007
Posted on Thursday, September 28 2006 @ 16:08 CEST by Thomas De Maesschalck