They are quick to emphasize that this revelation is not tantamount to a product announcement, but the provisions are there should they decided to release such a product.
On the subject of the die size of current 65nm parts, they say the relatively small reduction in die area from 90nm to 65nm is not the result of added L2 cache being placed into silicon and then deactivated in the 4800+ and 5000+ models we tested. Instead, the modest reduction in die size has origins in the esoterica of process technology and AMD's model of continuous, gradual improvement to its manufacturing techniques.
AMD 65nm L2 cache slower but with provisions for larger cache
Posted on Friday, Dec 22 2006 @ 16:18 CET by Thomas De Maesschalck