Posted on Friday, December 29 2006 @ 2:00 CET by Thomas De Maesschalck
The upcoming AMD Star processors
will arrive in the third quarter of 2007. The Star processors will feature support for DDR2-1066 memory and will feature new SSE4A instructions. The SSE4A instruction set is compatible with Intel's SSE4, it only lacks the Intel 64-bit instructions.
The new Star family includes quad-core Agena, mainstream dual-core Kuma, entry dual core Rana, and single-core Spica. In addition, the old K8 architecture has been renamed to Cities. The new Star microarchitecture has lots of improvements includes : Hyper-Transport 3.0 (from 2GT/s to 5.2GT/s), 32B Instruction Fetch, more precise Branch Prediction and Out-of-Order Load Execution, 4 Double Precision FLOPS/Cycle, Dual 128Bit SSE calculation, and Load per Cycle. At the same clock speed, the new microarchitecture would further push the performance to another high. It should be noted that AM2+ and AM2 is compatible to each other. For example, Altair can work in the existing Socket AM2 main board, the only need is BIOS upgrade. Yet Hyper-Transport will get only 2GHz in Socket AM2 main board as ver. 2.0. Furthermore, AM2+ main board is also designed to support AM3, according to AMD’s AM2r2 specification.
AMD hopes the Star processors will grab 10 percent of the total shipments in its first quarter. By Q4 2007 this should rise to 20% and by Q1 2008 Star should account for 60% of all AMD's processor shipments.
