Posted on Thursday, Jan 04 2007 @ 17:39 CET by Thomas De Maesschalck
At the International Solid State Circuits Conference (ISSCC) 2007 conference in February, Intel will present some information about its 80-core, floating-point-centric, Terascale prototype processor. This is a research project but it looks like it's going well enough to allow Intel to do a session about it t ISSSC.
For my part, I wonder if this has any relation to the whole Intel GPGPU skunkworks project that the Register has been on about recently. If Intel uses the Terascale chip's TSV (through silicon via) interconnect technology to stack a bunch of fast SRAM onto a cutting-edge GPU design, they may eat everyone's lunch.
On the AMD side of the fence, the quad-core Opteron gets its own session. Hopefully, AMD will release even more microarchitectural details on the new design, so that we can get a better sense of how it stacks up to Woodcrest.
More details over at ARS Technica
which also has more information about the IBM Power6 processor and a new Cell processor. Here's a short snip:
The POWER6TM microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications..