Posted on Friday, March 30 2007 @ 8:21 CEST by Thomas De Maesschalck
TSMC
announced it will start running its 55nm process technology on a prototype basis in May.
TSMC (Hsinchu, Taiwan) said the process is a 90 percent linear-shrink from its well established 65-nm technology including I/O and analog circuits, and that it would deliver "significant die cost savings from 65-nm, while offering the same speed and 10 to 20 percent lower power consumption."
In the first phase, the 55-nm logic family will be offered in the company's so called "CyberShuttle" program and include general purpose (GP) and consumer (GC) platforms. Initial production of the 55GP begins in May, followed later in the year by 55GC.
The company says that since the 55-nm process is a direct shrink, IP providers can leverage existing libraries and port their 65-nm designs with minimal risk and effort.
