Posted on Thursday, April 19 2007 @ 3:05 CEST by Thomas De Maesschalck
The Inq
has all the details on Intel's plans for the FSB bus. Here's a short snip:
As Charlie reported yesterday, Intel has taken another step forward: with their new QuickAssist technology and AAL (Accelerator Abstraction Layer) it opened up that FSB to others, for the first time - partly to offset the AMD Torrenza initiative (PCI-E on Geneseo simply can't do tight X87-like coprocessor-level integration as well as HyperTransport or CSI or plain FSB can do - think cache-coherent shared memory?), and partly to sell more of those expensive, upcoming Caneland four-socket, four-FSB chipsets.
Xilinx Virtex 5 high-end FPGA is the first one to have that FSB cell in-built, ready to plug into the socket 604 or LGA771. Both Xiling and Intel guys on the IDF Beijing booth were confident that FSB1066 is a done deal, but no confirmation if, say, I could use one at FSB1600 speed levels in the second CPU socket of the dual-FSB SeaBurg chipset.
In my mind, there are three possible uses for this socket - knowing well it's basically a 'pilot' test till the CSI versions sit in 18 months from now: computation (mainly FP) accelerators, commercial ( XML / crypto / search / data mining) accelerators, and communication / interconnect accelerators. An FPGA can't compete against ASIC-level GPUs or Intel Terascale chip (the latter could be a good candidate to fit inside such FSB socket), but, being programmable at the gate level, it can offload some specific routines at hardwiring speed, and tackle both computation and commercial algorithms easier...
