''Intel to delay its Tejas processor to Q2 2005''

Intel’s code-named Tejas microprocessor, the fourth-generation NetBurst CPUs, will have core-speeds at around 4.0GHz – 4.20GHz, probably a faster Quad Pumped Bus, tangibly enlarged caches (24KB L1 cache, 16K uOps Trace Cache, 1MB L2 cache [probably 2MB for 65nm version]), a more efficient branch prediction mechanism, a new set of instructions known as “Tejas New Instructions” as well as improved Hyper-Threading organization. In addition, the Tejas may enable long-awaited 64-bit enhancements to x86 architecture or may increase the number of executive units.

Instead of Tejas, Intel will kick-off 4.20GHz Pentium 4 Prescott chip in Q1 2005, the source indicated.

First Tejas processors will be made using 90nm fabrication technology, while CPUs due out later will be manufactured at 65nm nodes. Nevertheless, there are rumours that Intel will use “another”, improved, version of its Strained Silicon technology to produce Tejas chips in early 2005. According to what was told by analysts familiar with the matter, Intel will change dielectric it uses in transistors with its next-generation process.

Provided that the information about revamped manufacturing technology for Tejas processors is correct, its delay may mean that Intel is concentrated on making the best technology possible to provide excellent frequency headroom amid reasonable power consumption by upcoming chips. On the other hand, delay of Tejas means Intel is pretty confident in Prescott and expects its first desktop 90nm part to be powerful enough for securing Intel’s position until Q2 2005.