TSMC today announced it has developed the first 32-nanometer (nm) technology that supports both analog and digital functionality. The company made its announcement through a paper presented at today’s IEEE International Electron Devices Meeting in Washington, DC. The paper also revealed that the company had proven the full functionality of the 2Mb SRAM test chip with the smallest bit-cell at the 32nm node.
This leading edge technology is optimized for low power, high density and manufacturing margins with optimal process complexity. Low power technology integrated with high density SRAM, low standby transistors, analog and RF functions, and copper and low-k interconnects is ideal for system on chip (SoC) devices targeted in mobile applications. TSMC plans to provide complete digital, analog and RF functions, and high density memory capabilities at 32nm node.
Noteworthy in the announcement is the fact that this is the first 32nm low-power technology that did not have to resort to high-k gate dielectric and metal gates to achieve its performance characteristics. In addition, a 0.15um² high density SRAM cell has been realized by 193nm immersion lithography using double patterning approach.
TSMC shows off 32nm SRAM
Posted on Wednesday, Dec 12 2007 @ 05:05 CET by Thomas De Maesschalck