The HyperTransport Technology Consortium today announced version 2.0 of HyperTransport.
The HyperTransport Release 2.0 Specification introduces three more powerful bus speeds and mapping to PCI Express, an emerging I/O interconnect architecture. HyperTransport's speed capability extends from the 1.6 Giga Transfers/second (GT/s) of Release 1.1 Specification to 2.0, 2.4, and 2.8 GT/s using dual-data rate clocks at 1.0, 1.2, and 1.4 Gigahertz, delivering a maximum aggregate bandwidth of 22.4 Gigabytes/second. The electrical protocols supporting the new clock rates are backward compatible with all previous versions of the HyperTransport electrical specifications.
"These new specifications are in response to HyperTransport Consortium's members expectation of backward compatibility with Release 1.05 and Release 1.1 Specifications along with state-of-the-art performance," noted Brian Holden, Chair of the Technical Working Group, responsible for the development of the technical specification. "We achieved our goal of successfully increasing data throughput without a major rework of the basic electrical specification."
"Release 2.0 Specification confirms the significant contribution that HyperTransport has been making to the industry over recent years," said Gabriele Sartori, President of the HyperTransport Technology Consortium. "Our technology empowers leading edge products like Microsoft's Xbox, Apple's Power Mac G5, Cisco's high-end routers, IBM's and Sun Microsystems's servers, notebooks and Tablet PC's based on Transmeta's Efficeon-processor, and all AMD's Athlon64- and Opteron-based PCs, servers and supercomputers."