Explaining Core 2's FSB, RAM, and bandwidth

Posted on Wednesday, January 23 2008 @ 8:15 CET by Thomas De Maesschalck

Icrontic.com has a crash course in the workings of the Core 2's front side bus, memory, and bandwidth. Aimed at novice overclockers, or anyone wondering why Intel rigs don't overclock like the Athlons of the past, the guide breaks down in plain English what could otherwise be a confusing, muddled topic.

"Today, Icrontic serves up a crash-course in the mysterious relationship of the Core 2 front side bus, RAM and bandwidth. The nature of the Core 2's design may be baffling, particularly to users exiting the era of synchronized Athlon XP buses, and we intend to cut through the haze and serve it straight just as we like to."

Check it out over here.

About the Author

Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.

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