Intel Itanium "Madison" 9MB L3 cache on track for Q3 2004 launch

Posted on Wednesday, Apr 21 2004 @ 23:20 CEST by Thomas De Maesschalck
In contrast to earlier news Intel's new high-end 64-bit Itanium 2 with 9MB L3 cache is on-track for launch in Q3 2004. There appear to be two versions : one with 400MHz and one with a 667MHz bus, respectively launched for Q3 2004 and Q1 2005.
Nowadays high-end Itanium 2 lineup from Intel includes 1.50GHz, 1.40GHz and 1.30GHz models with 6MB, 4MB and 3MB L3 cache respectively. All the current chips use 400MHz Quad Pumped Bus, 667MHz PSB to be introduced early next year will be the first bump for MP Itanium’s bus speed that is likely to give a strong boost for performance of IA64 MP servers. However, even earlier Intel is expected to boost the PSB clock-rate of Itanium 2 processors designed for 2P servers: in Q4 2004 a cut-down flavour of Madison 9M, chip code-named Fanwood, will get a 533MHz Quad Pumped Bus.

667MHz will be a magic number for Intel processors designed for multi-processor servers. The company’s next-generation Xeon MP processors with Enhanced Memory 64 Technology code-named Potomac will also sport 667MHz processor system bus. The company recently confirmed plans to unify Itanium and Xeon platforms so that both processors would fit into one socket. But the chipmaker does not indicate when exactly this happens.
Source: X-bit Labs


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Thomas De Maesschalck

Thomas has been messing with computer since early childhood and firmly believes the Internet is the best thing since sliced bread. Enjoys playing with new tech, is fascinated by science, and passionate about financial markets. When not behind a computer, he can be found with running shoes on or lifting heavy weights in the weight room.



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