Rambus today announced the availability of a broad family of double data rate (DDR) memory controller interface cells and services. Providing support for mainstream DDR1 and DDR2 up to 800MHz data rates and graphics DDR, including GDDR1, GDDR2, and GDDR3 up to 1600MHz data rates, Rambus DDR memory controller interface cells are full-featured drop-in physical layer (PHY) cells. The interface cells use proven technology that allow customers to dramatically improve time to market, minimize design risk and avoid potential re-spin costs. Rambus also offers system engineering services to further accelerate time to market, and ensure the interface operates at high frequency in the system environment. Rambus DDR interface solutions are ideal for a broad range of applications, from consumer multimedia and graphics systems to mainstream PCs and servers.
"As DDR memory interfaces become faster and as a result more challenging to design, a growing number of customers are requesting proven solutions," said Laura Stark, vice president of the Memory Interface Division at Rambus. "By using Rambus DDR solutions for the memory interface, chip designers can focus on other critical portions of the chip. This new solution, along with RDRAM and XDR memory interfaces, rounds out our product portfolio and provides a memory interface for any level of performance need."
Rambus DDR memory controller interfaces are complete interface cells instead of technology building blocks, such as I/O pads and delay lock loops (DLLs) that engineers must assemble, integrate and verify on their own. By incorporating Rambus's drop-in DDR memory controller interface cells into their chip designs, customers can save an estimated six-to-nine months of development time and potentially millions of dollars by avoiding costly chip re-spins and lost revenues from being late to market. As with all Rambus interface solutions, Rambus DDR interface cells are designed to integrate seamlessly into silicon, and provide improved time-to-market, lower design risk, higher performance, and lower total cost.
Additionally, Rambus is the only company to provide DDR memory controller interfaces with an optional performance mode supporting XDR DRAM, enabling a two-to-eight times increase in system memory bandwidth. Using this capability, customers can develop a single chip that spans multiple price/performance points depending on which memory type is connected.
Rambus DDR interface circuits are designed for a wide variety of standard CMOS processes, such as 90nanometer, 0.13-micron and 0.18-micron, and are available immediately on 0.13-micron process. Rambus DDR memory controller interfaces for consumer and graphics applications are available now, and those for main memory applications will be available soon.
Rambus will host a web seminar on May 20, 2004 at 10:00 a.m. PDT to outline its DDR interface cells and services. Additional information about the Rambus family of DDR memory controller interfaces can be found at here
Rambus announces DDR and GDDR memory controllers
Posted on Thursday, May 13 2004 @ 18:14 CEST by Thomas De Maesschalck