The main micro-architectural enhancements for Nehalem that Intel has discussed so far is increased parallelism – the new microprocessors will be able to execute 33% more concurrent micro-ops at the same time. Additional improvements include faster unaligned cache accesses and faster synchronization primitives. In order to exclude situations when execution units stand idle, Intel also implemented new 2nd level branch predictor.
Another key enhancement of Intel Nehalem is completely redesigned cache sub-system. The new chips will feature 2nd level 512 entry translation look-aside buffer (in addition to 1st level TLB) in order to further reduce the so-called TLB miss rate, a completely new feature on x86 microprocessors. In addition, Intel Nehalem processors (at least, in certain implementations) will have three-level cache hierarchy: 64KB L1 (32KB for data, 32KB for instructions), 256KB L2 cache per core, 8MB L3 cache per processor. Traditionally, Intel chips use inclusive cache policy.
The world’s largest maker of x86 microprocessors also reiterated that its high-end Nehalem microprocessors will have from 2 to 8 cores, triple-channel DDR3 memory controller (with up to 1333MHz clock-speed supported initially), will use Quick Path Interconnect (QPI) bus and will support multi-threading technology similar with Intel Hyper-Threading that was first unveiled back in 2002 as well as SSE4.2 instructions.
Key improvements in Intel's Core i7 architecture
Posted on Sunday, Aug 10 2008 @ 01:29 CEST by Thomas De Maesschalck