Posted on Monday, February 21 2011 @ 19:54 CET by Thomas De Maesschalck
AMD
will talk about its upcoming processor designs at ISCC 2011:
ISSCC 2011, happening from 2/20 – 2/24, will be no different. AMD is releasing information about a few of its current and upcoming products, and we’ll be using AMD’s Bulldozer blog throughout the course of next week to update you on some of the details being disclosed for the first time about AMD’s newest core design, “Bulldozer.” If you want access to the complete conference proceedings, please register for the conference to receive them. Here are the basic areas being discussed:
* Design Solutions for the “Bulldozer” 32nm: Showcasing AMD’s 32nm technology and leading-edge design techniques, this session will discuss the power savings, performance improvements and new competitive features offered up by “Bulldozer”. Session date and time: Monday, 2/21, 3:15 p.m.
* 40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD “Bulldozer”: This session will be used to dive even further into the Bulldozer architecture to understand its out-of-order execution set and how the integer unit performs. Session date and time: Monday, 2/21, 3:45 p.m.
* An 8MB Level-3 Cache in 32nm SOI with Column-Select Aliasing: Interested in the technical and design details of “Orochi,” AMD’s upcoming high-end desktop and server processor? This session will discuss the new technologies and power-saving features used in the design. Session date and time: Tuesday, 2/22, 2:30 p.m.
* A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computer Devices: This session will look at AMD’s first generation Fusion processor, the AMD E-Series APU, formerly codenamed “Zacate,” which combines the power of an x86 CPU and AMD RadeonTM graphics manufactured on a 40nm die. You’ll learn how it was designed and how to optimize performance and energy usage. Session date and time: Tuesday, 2/22, 4:15 p.m.
