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Rambus details new memory clocking approach

Posted on Thursday, June 16 2011 @ 18:42:09 CEST by


EE Times reports Rambus revealed a new fast power-on, low-power clocking technology for a new class of memory devices.
The technology, described at the VLSI Circuit Symposium in Kyoto, Japan, is capable of transitioning from a zero-power idle state to a 5+ Gb/s data transfer rate in approximately 5 nanoseconds (ns) while achieving active power of only 2.4mW/Gb/s, according to Rambus (Los Altos, Calif.).

The new approach, developed by Rambus Labs, uses a calibrated feed-forward architecture to achieve extremely fast turn-on and turn-off, simplifying the system design and significantly reducing the overall system power requirements, according to Rambus.

The technology is implemented in a 40-nm low-power CMOS process, according to Rambus.




 



 

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