The Itanium "Poulson" 12-wide issue microprocessor has eight multi-threaded cores with new micro-architecture and a new version of Hyper-Threading technology, a ring-based system interface and combined 50MB cache on the die. Among the key core architecture improvements, Intel names new floating point pipeline, new data ant instruction popes, new instruction buffer and doubled max execution width (6 to 12). The innovations allow Intel to increase performance per watt, increase instruction throughput and boosted RAS coverage.
Intel tells more about Poulson Itanium chip
Posted on Wednesday, August 24 2011 @ 21:57 CEST by Thomas De Maesschalck