Samsung's Daeyeal Lee delivered a paper describing the company's 64-Gbit multi-level cell (MLC) NAND device implemented in sub-20-nm technology. The device features a 533-megabit-per-second DDR interface achieved by implementing a wave-pipeline architecture, Lee said. The chip also makes use of new techniques to overcome floating-gate coupling interference and mitigate program disturbance, Lee said.
According to Lee, the use of the new schemes, known as correction-before-recoupling reprogram and P3 pattern pre-pulse scheme, results in a 21 percent lower bit error rate compared with conventional techniques. Lee described another technique, inhibit-channel-coupling-reduction, for mitigating program disturbance in the chip.
NAND makers detail sub-20nm memory
Posted on Thursday, February 23 2012 @ 19:05 CET by Thomas De MaesschalckEE Times reports Samsung, Toshiba and SanDisk engineers revealed details on their 19nm technology at the International Solid-State Circuit Conference (ISSCC) on Wednesday. You can read all the details over here.
